1) Field of the Invention
The invention relates to planarization of the dielectric layers within the multilayer metallization which separate conductive layers. The planarization involves nonetchback spin-on-glass techniques.
2) Description of the Prior Art
The top surface of semiconductor substrates is irregular because of the formation of gate electrodes, resistors, capacitors, conductors, etc. Planarizing layers, such as spin on glass layers, are used to smooth the surface so that subsequent metal and insulation layers may be formed. Planarizing layers are often formed in a three layer spin-on-glass sandwich structure comprising: (1) a bottom first insulating layer, (2) a center spin on glass (SOG) layer, and (3) a top second insulating layer. A problem with the current spin-on-glass sandwich structures/processes is that the first insulating layer and the spin-on-glass layer separate or delaminate. This delamination causes the reliability and yield problems with the devices.
FIG. 1 shows a planarized multilayer metallization structure. There is shown a semiconductor substrate 10 having N type diffused regions 12 therein. Polysilcon gate structures composed of the gate dielectric 14 and gate electrode or conductor 16 are formed on the surface of the substrate 10 and cooperate with the diffused regions to act as MOSFET devices. An insulating or dielectric layer 18 layer is formed thereover by conventional means. A conductor layer 20 has been deposited and patterned by lithography and etching. The spin-on-glass sandwich layer 22, 24, 26 composed of: (1) a first silicon oxide like layer 22, (2) spin-on-glass (SOG) layer 24 and (3) a second silicon oxide like layer 26. A delamination area 30 is shown where the spin-on-glass layer 22 delaminates from first silicon oxide layer 22. The spin-on-glass layer 24 and layers formed above the spin-on-glass layer detach. The delamination area 30 is often caused by shear stress exerted by the package. This delamination problem can be detected in standard temperature cycle tests where the air temperature is varied between -65.degree. C. and 150.degree. C. The delamination problem causes yield and reliability problems, such as complete circuit fails caused by the missing circuits above the delmaination area 30.
U.S. Pat. No. 5,003,062, Yen describes an improved method to form a Spin-on-Glass sandwich using more than one SOG layer deposition and curing step to build the required middle SOG layer thickness. However, the patent does not address the delamination problem between the first silicon oxide layer and the SOG layer.